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| ispGDX 160V/VA TM In-System Programmable 3.3V Generic Digital Crosspoint TM Features * IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY -- Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement -- "Any Input to Any Output" Routing -- Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation -- Space-Saving PQFP and BGA Packaging -- Dedicated IEEE 1149.1-Compliant Boundary Scan Test * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- 3.3V Core Power Supply -- 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay* -- 250MHz Maximum Clock Frequency* -- TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable)* -- Low-Power: 16.5mA Quiescent Icc* -- 24mA IOL Drive with Programmable Slew Rate Control Option -- PCI Compatible Drive Capability* -- Schmitt Trigger Inputs for Noise Immunity -- Electrically Erasable and Reprogrammable -- Non-Volatile E2CMOS Technology * ispGDXVTM OFFERS THE FOLLOWING ADVANTAGES -- 3.3V In-System Programmable Using Boundary Scan Test Access Port (TAP) -- Change Interconnects in Seconds * FLEXIBLE ARCHITECTURE -- Combinatorial/Latched/Registered Inputs or Outputs -- Individual I/O Tri-state Control with Polarity Control -- Dedicated Clock/Clock Enable Input Pins (four) or Programmable Clocks/Clock Enables from I/O Pins (40) -- Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns) -- Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX -- Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins -- Outputs Tri-state During Power-up ("Live Insertion" Friendly) * DESIGN SUPPORT THROUGH LATTICE'S ispGDX DEVELOPMENT SOFTWARE -- MS Windows or NT / PC-Based or Sun O/S -- Easy Text-Based Design Entry -- Automatic Signal Routing -- Program up to 100 ISP Devices Concurrently -- Simulator Netlist Generation for Easy Board-Level Simulation * "VA" Version Only Functional Block Diagram I/O Pins D ISP Control I/O Pins C I/O Pins A I/O Cells Global Routing Pool (GRP) I/O Cells Boundary Scan Control I/O Pins B Description The ispGDXV/VA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including: * Multi-Port Multiprocessor Interfaces * Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX) * Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.) * Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of 3.5ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs Copyright (c) 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com July 2000 gdx160va_04 1 Specifications ispGDX160V/VA Description (Continued) found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock (CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output. A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of 2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of I/O pins. CLKEN disables the register clock when CLKEN = 0. Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. In keeping with its data path application focus, the ispGDXV devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for noise immunity. These connections are programmed into the device using non-volatile E2CMOS technology. Non-volatile technology means the device configuration is saved even when the power is removed from the device. Table 1. ispGDXV Family Members ispGDXV/VA Device ispGDX80VA I/O Pins I/O-OE Inputs* I/O-CLK / CLKEN Inputs* I/O-MUXsel1 Inputs* I/O-MUXsel2 Inputs* Dedicated Clock Pins** EPEN TOE BSCAN Interface RESET Pin Count/Package 80 20 20 20 20 2 1 1 4 1 100-Pin TQFP ispGDX160V/VA ispGDX240VA 160 40 40 40 40 4 1 1 4 1 240 60 60 60 60 4 1 1 4 1 In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. That is, any I/O pin configured as an input can drive one or more I/O pins configured as outputs. The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode). Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive. On the ispGDXVA, each I/O pin is individually programmable for 3.3V or 2.5V output levels as described later. Programmable output slew rate control can be defined independently for each I/O pin to reduce overall ground bounce and switching noise. All I/O pins are equipped with IEEE1149.1-compliant Boundary Scan Test circuitry for enhanced testability. In addition, in-system programming is supported through the Test Access Port via a special set of private commands. The ispGDXV I/Os are designed to withstand "live insertion" system environments. The I/O buffers are disabled during power-up and power-down cycles. When designing for "live insertion," absolute maximum rating conditions for the Vcc and I/O pins must still be met. 208-Pin PQFP 388-Ball fpBGA 208-Ball fpBGA 272-Ball BGA * The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to 25% of the I/Os. ** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and CLKEN3 respectively in all devices. 2 Specifications ispGDX160V/VA Architecture The ispGDXV/VA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI devices, there are no programmable logic arrays on the device. Control signals for OEs, Clocks/Clock Enables and MUX Controls must come from designated sets of I/O pins. The polarity of these signals can be independently programmed in each I/O cell. Each I/O cell drives a unique pin. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O pins (I/O-OE set). The I/O-OE set consists of 25% of the total I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. In-system programming is accomplished through the standard Boundary Scan protocol. The various I/O pin sets are also shown in the block diagram below. The A, B, C, and D I/O pins are grouped together with one group per side. I/O Architecture Each I/O cell contains a 4:1 dynamic MUX controlled by two select lines as well as a 4x4 crossbar switch controlled by software for increased routing flexiability (Figure 1). The four data inputs to the MUX (called M0, M1, M2, and M3) come from I/O signals in the GRP and/or adjacent I/O cells. Each MUX data input can access one quarter of the total I/Os. For example, in a 160 I/O ispGDXV, each data input can connect to one of 40 I/O pins. MUX0 and MUX1 can be driven by designated I/O pins called MUXsel1 and MUXsel2. Each MUXsel input covers 25% of the total I/O pins (e.g. 40 out of 160). MUX0 and MUX1 can be driven from either MUXsel1 or MUXsel2. Figure 1. ispGDXV/VA I/O Cell and GRP Detail (160 I/O Device) Logic "0" Logic "1" 160 I/O Inputs I/OCell 0 I/O Cell 159 I/O Cell 1 I/O Cell 158 E2CMOS Programmable Interconnect From MUX Outputs of 2 Adjacent I/O Cells N+2 I/O Group A I/O Group B I/O Group C I/O Group D N+1 4x4 Crossbar Switch * * * To 2 Adjacent I/O Cells above Bypass Option Register or Latch 4-to-1 MUX M0 M1 M2 M3 MUX0 MUX1 To 2 Adjacent I/O Cells below Prog. Prog. Pull-up Bus Hold Latch (VCCIO) A B D CLK CLK_EN Reset C R Prog. Open Drain 2.5V/3.3V Output Prog. Slew Rate I/O Pin Q N-1 N-2 * * * * * * From MUX Outputs of 2 Adjacent I/O Cells Boundary Scan Cell I/O Cell N * * * I/O Cell 78 ****** I/O Cell 81 I/O Cell 79 80 I/O Cells 160 Input GRP Inputs Vertical Outputs Horizontal Global Y0-Y3 Reset Global Clocks / Clock_Enables I/O Cell 80 80 I/O Cells ispGDXV/VA architecture enhancements over ispGDX (5V) 3 Specifications ispGDX160V/VA I/O MUX Operation MUX1 0 0 1 1 MUX0 0 1 1 0 Data Input Selected M0 M1 M2 M3 Device ispGDX80VA ispGDX160V/VA ispGDX240VA Normal I/O Cells B9-B0, A19-A0, D19-D10 B19-B0, A39-A0, D39-D20 B29-B0, A59-A0, D59-D30 Reflected I/O Cells B10-B19, C0-C19, D0-D9 B20-B39, C0-C39, D0-D19 B30-B59, C0-C59, D0-D29 allow adjacent I/O cell outputs to be directly connected without passing through the global routing pool. The relationship between the [N+i] adjacent cells and A, B, C and D inputs will vary depending on where the I/O cell is located on the physical die. The I/O cells can be grouped into "normal" and "reflected" I/O cells or I/O "hemispheres." These are defined as: Flexible mapping of MUXselx to MUXx allows the user to change the MUX select assignment after the ispGDXV/ VA device has been soldered to the board. Figure 1 shows that the I/O cell can accept (by programming the appropriate fuses) inputs from the MUX outputs of four adjacent I/O cells, two above and two below. This enables cascading of the MUXes to enable wider (up to 16:1) MUX implementations. The I/O cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. As shown in Figure 1, when the input control MUX of the register/ latch selects the "A" path, the register/latch gets its inputs from the 4:1 MUX and drives the I/O output. When selecting the "B" path, the register/latch is directly driven by the I/O input while its output feeds the GRP. The programmable polarity Clock to the latch or register can be connected to any I/O in the I/O-CLK/CLKEN set (onequarter of total I/Os) or to one of the dedicated clock input pins (Yx). The programmable polarity Clock Enable input to the register can be programmed to connect to any of the I/O-CLK/CLKEN input pin set or to the global clock enable inputs (CLKENx). Use of the dedicated clock inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output mode may be implemented by a dedicated architecture bit and bypass MUX. I/O cell output polarity can be programmed as active high or active low. Table 2 shows the relationship between adjacent I/O cells as well as their relationship to direct MUX inputs. Note that the MUX expansion is circular and that I/O cell B20, for example, draws on I/Os B19 and B18, as well as B21 and B22, even though they are in different hemispheres of the physical die. Table 2 shows some typical cases and all boundary cases. All other cells can be extrapolated from the pattern shown in the table. Figure 2. I/O Hemisphere Configuration of ispGDX160V/VA I/O cell 0 I/O cell 159 D39 A0 I/O cell index increases in this direction D20 D19 D0 I/O cell index increases in this direction C39 MUX Expander Using Adjacent I/O Cells The ispGDXV/VA allows adjacent I/O cell MUXes to be cascaded to form wider input MUXes (up to 16 x 1) without incurring an additional full Tpd penalty. However, there are certain dependencies on the locality of the adjacent MUXes when used along with direct MUX inputs. Adjacent I/O Cells Expansion inputs MUXOUT[n-2], MUXOUT[n-1], MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable for each I/O cell MUX. These expansion inputs share the same path as the standard A, B, C and D MUX inputs, and Direct and Expander Input Routing Table 2 also illustrates the routing of MUX direct inputs that are accessible when using adjacent I/O cells as inputs. Take I/O cell D23 as an example, which is also shown in Figure 3. A39 C0 B0 B19 I/O cell 79 B20 I/O cell 80 B39 4 Specifications ispGDX160V/VA Figure 3. Adjacent I/O Cells vs. Direct Input Path for ispGDX160V/VA, I/O D23 ispGDX160V/VA I/O Cell I/O Group A D21 MUX Out I/O Group B D22 MUX Out I/O Group C D24 MUX Out I/O Group D D25 MUX Out 4x4 Crossbar Switch S1 S0 .m0 .m1 .m2 .m3 Special Features Slew Rate Control All output buffers contain a programmable slew rate control that provides software-selectable slew rate options. Open Drain Control D23 It can be seen from Figure 3 that if the D21 adjacent I/O cell is used, the I/O group "A" input is no longer available as a direct MUX input. The ispGDXV/VA can implement MUXes up to 16 bits wide in a single level of logic, but care must be taken when combining adjacent I/O cell outputs with direct MUX inputs. Any particular combination of adjacent I/O cells as MUX inputs will dictate what I/O groups (A, B, C or D) can be routed to the remaining inputs. By properly choosing the adjacent I/O cells, all of the MUX inputs can be utilized. Table 2. Adjacent I/O Cells (Mapping of ispGDX160V/VA) Data A/ Data B/ Data C/ Data D/ MUXOUT MUXOUT MUXOUT MUXOUT B20 B21 B22 Reflected I/O Cells B23 D16 D17 D18 D19 D20 D21 D22 Normal I/O Cells D23 B16 B17 B18 B19 B22 B23 B24 B25 D18 D19 D20 D21 D18 D19 D20 D21 B14 B15 B16 B17 B21 B22 B23 B24 D17 D18 D19 D20 D19 D20 D21 D22 B15 B16 B17 B18 B19 B20 B21 B22 D15 D16 D17 D18 D21 D22 D23 D24 B17 B18 B19 B20 B18 B19 B20 B21 D14 D15 D16 D17 D22 D23 D24 D25 B18 B19 B20 B21 All output buffers provide a programmable Open-Drain option which allows the user to drive system level reset, interrupt and enable/disable lines directly without the need for an off-chip Open-Drain or Open-Collector buffer. Wire-OR logic functions can be performed at the printed circuit board level. Pull-up Resistor All pins have a programmable active pull-up. A typical resistor value for the pull-up ranges from 50k to 80k. Output Latch (Bus Hold) All pins have a programmable circuit that weakly holds the previously driven state when all drivers connected to the pin (including the pin's output driver as well as any other devices connected to the pin by external bus) are tristated. ispGDX160VA New Features Unique to the ispGDX160VA are user-programmable I/Os supporting either 3.3V or 2.5V output voltage level options. The ispGDX160VA uses a VCCIO pin to provide the 2.5V reference voltage when used. The ispGDX160VA VCCIO pin occupies the same location as VCC on the ispGDX160V, allowing drop-in replacement. The ispGDX160VA offers improved performance by reducing fanout delays and has PCI compatible drive capability. Only the ispGDX160VA is available in the fastest (3.5ns) Commercial speed grade and in -5,-7, and -9ns Industrial grades in all packages. The ispGDX160VA has a device ID different from the ispGDX160V requiring that the latest Lattice download software be used for programming and verification. Although the ispGDX160VA and ispGDX160V are functionally equivalent, they are not 100% JEDEC compatible. All design files must be recompiled targeting the ispGDX160VA. 5 Specifications ispGDX160V/VA Applications The ispGDXV/VA Family architecture has been developed to deliver an in-system programmable signal routing solution with high speed and high flexibility. The devices are targeted for three similar but distinct classes of endsystem applications: Programmable Switch Replacement (PSR) Includes solid-state replacement and integration of mechanical DIP Switch and jumper functions. Through in-system programming, pins of the ispGDXV/VA devices can be driven to HIGH or LOW logic levels to emulate the traditional device outputs. PSR functions do not require any input pin connections. These applications actually require somewhat different silicon features. PRSI functions require that the device support arbitrary signal routing on-chip between any two pins with no routing restrictions. The routing connections are static (determined at programming time) and each input-to-output path operates independently. As a result, there is little need for dynamic signal controls (OE, clocks, etc.). Because the ispGDXV/VA device will interface with control logic outputs from other components (such as ispLSI or ispMACH) on the board (which frequently change late in the design process as control logic is finalized), there must be no restrictions on pin-to-pin signal routing for this type of application. PDP functions, on the other hand, require the ability to dynamically switch signal routing (MUXing) as well as latch and tri-state output signals. As a result, the programmable interconnect is used to define possible signal routes that are then selected dynamically by control signals from an external MPU or control logic. These functions are usually formulated early in the conceptual design of a product. The data path requirements are driven by the microprocessor, bus and memory architecture defined for the system. This part of the design is the earliest portion of the system design frozen, and will not usually change late in the design because the result would be total system and PCB redesign. As a result, the ability to accommodate arbitrary any pin-to-any pin rerouting is not a strong requirement as long as the designer has the ability to define his functions with a reasonable degree of freedom initially. As a result, the ispGDXV/VA architecture has been defined to support PSR and PRSI applications (including bidirectional paths) with no restrictions, while PDP applications (using dynamic MUXing) are supported with a minimal number of restrictions as described below. In this way, speed and cost can be optimized and the devices can still support the system designer's needs. The following diagrams illustrate several ispGDXV/VA applications. Programmable, Random Signal Interconnect (PRSI) This class includes PCB-level programmable signal routing and may be used to provide arbitrary signal swapping between chips. It opens up the possibilities of programmable system hardware. It is characterized by the need to provide a large number of 1:1 pin connections which are statically configured, i.e., the pin-to-pin paths do not need to change dynamically in response to control inputs. Programmable Data Path (PDP) This application area includes system data path transceiver, MUX and latch functions. With today's 32- and 64-bit microprocessor buses, but standard data path glue components still relegated primarily to eight bits, PCBs are frequently crammed with a dozen or more data path glue chips that use valuable real estate. Many of these applications consist of "on-board" bus and memory interfaces that do not require the very high drive of standard glue functions but can benefit from higher integration. Therefore, there is a need for a flexible means to integrate these on-board data path functions in an analogous way to programmable logic's solution to control logic integration. Lattice's CPLDs make an ideal control logic complement to the ispGDXV/VA in-system programmable data path devices as shown below. Figure 4. ispGDXV/VA Complements Lattice CPLDs Address Inputs (from P) Control Inputs (from P) Data Path Bus #1 ISP/JTAG Buffers / Registers Interface Control Outputs State Machines ispLSI/ ispMACH Device Decoders ispGDXV/VA Device Buffers / Registers Configuration (Switch) Outputs System Clock(s) Data Path Bus #2 6 Specifications ispGDX160V/VA Applications (Continued) Figure 5. Address Demultiplex/Data Buffering Designing with the ispGDXV/VA As mentioned earlier, this architecture satisfies the PRSI class of applications without restrictions: any I/O pin as a single input or bidirectional can drive any other I/O pin as output. For the case of PDP applications, the designer does have to take into consideration the limitations on pins that can be used as control (MUX0, MUX1, OE, CLK) or data (MUXA-D) inputs. The restrictions on control inputs are not likely to cause any major design issues because the input possibilities span 25% of the total pins. The MUXA-D input partitioning requires that designers consciously assign pinouts so that MUX inputs are in the appropriate, disjoint groups. For example, since the MUXA group includes I/O0-39 (160 I/O device), it is not possible to use I/O0 and I/O9 in the same MUX function. As previously discussed, data path functions will be assigned early in the design process and these restrictions are reasonable in order to optimize speed and cost. XCVR I/OA I/OB MUXed Address Data Bus Buffered Data OEA OEB To Memory/ Peripherals Control Bus Address Latch D Q Address CLK Figure 6. Data Bus Byte Swapper D0-7 XCVR I/OA I/OB D0-7 XCVR I/OA I/OB OEA OEB User Electronic Signature Data Bus B Data Bus A OEA OEB XCVR D8-15 I/OA I/OB D8-15 XCVR I/OA I/OB OEA OEB OEA OEB The ispGDXV/VA Family includes dedicated User Electronic Signature (UES) E2CMOS storage to allow users to code design-specific information into the devices to identify particular manufacturing dates, code revisions, or the like. The UES information is accessible through the boundary scan programming port via a specific command. This information can be read even when the security cell is programmed. Control Bus Security Figure 7. Four-Port Memory Interface 4-to-1 16-Bit MUX Bidirectional Port #1 OE1 Port #2 OE2 Port #3 OE3 Bus 2 The ispGDXV/VA Family includes a security feature that prevents reading the device program once set. Even when set, it does not inhibit reading the UES or device ID code. It can be erased only via a device bulk erase. To Memory Memory Port OEM Bus 4 Bus 3 SEL0 Note: All OE and SEL lines driven by external arbiter logic (not shown). Bus 1 Port #4 OE4 SEL1 7 Specifications ispGDX160VA Absolute Maximum Ratings 1,2 Supply Voltage Vcc ................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C 1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Conditions SYMBOL PARAMETER Supply Voltage I/O Reference Voltage Commercial Industrial TA = 0C to +70C TA = -40C to +85C MIN. 3.00 3.00 2.3 MAX. 3.60 3.60 3.60 UNITS V V V VCC VCCIO Table 2-0005/gdx160va Capacitance (TA=25oC, f=1.0 MHz) SYMBOL PARAMETER I/O Capacitance PACKAGE TYPE PQFP BGA, fpBGA PQFP BGA, fpBGA TYPICAL 7 10 8 10 UNITS pf pf pf pf TEST CONDITIONS VCC = 3.3V, VI/O = 2.0V VCC = 3.3V, VY = 2.0V Table 2-0006/gdx160va C1 C2 Dedicated Clock Capacitance Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM -- UNITS Cycles 8 Specifications ispGDX160VA Switching Test Conditions Figure 8. Test Load Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to VCCIO(MIN) < 1.5ns 10% to 90% VCCIO(MIN)/2 VCCIO(MIN)/2 See Figure 8 VCCIO R1 Device Output R2 CL* Test Point 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (See Figure 8) 3.3V TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL+0.5V Slow Slew R1 153 R2 134 134 R1 156 2.5V R2 CL 144 35pF 144 35pF *CL includes Test Fixture and Probe Capacitance. 0213D 153 156 134 144 35pF 5pF 5pF 35pF 153 156 C D Table 2-0004A/gdx160va DC Electrical Characteristics for 3.3V Range1 Over Recommended Operating Conditions SYMBOL PARAMETER I/O Reference Voltage Input Low Voltage Input High Voltage Output Low Voltage CONDITION - VOH VOUT or VOUT VOL (MAX) VOH VOUT or VOUT VOL(MAX) VCC = VCC (MIN) VCC = VCC (MIN) IOL = +100A IOL = +24mA IOH = -100A IOH = -12mA MIN. 3.0 -0.3 2.0 - - 2.8 2.4 TYP. - - - - - - - MAX. UNITS 3.6 0.8 5.25 0.2 0.55 - - V V V V V V V VCCIO VIL VIH VOL VOH Output High Voltage 1. I/O voltage configuration must be set to VCC. Table 2-0007/gdx160va 9 Specifications ispGDX160VA DC Electrical Characteristics for 2.5V Range1 Over Recommended Operating Conditions SYMBOL PARAMETER I/O Reference Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CONDITION - VOH(MIN) VOUT or VOUT VOL(MAX) VOH(MIN) VOUT or VOUT VOL(MAX) VCCIO=MIN, IOL = 100A VCCIO=MIN, IOL = 8mA VCCIO=MIN, IOH = -100A VCCIO=MIN, IOH = -8mA MIN. 2.3 -0.3 1.7 - - 2.1 1.8 TYP. - - - - - - - MAX. UNITS 2.7 0.7 5.25 0.2 0.6 - - V V V V V V V 2.5V/gdx160va VCCIO VIL VIH VOL VOH 1. I/O voltage configuration must be set to VCCIO. DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pullup Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points Output Short Circuit Current Quiescent Power Supply Current Dynamic Power Supply Current per Input Switching Maximum Continuous I/O Pin Sink Current Through Any GND Pin CONDITION 0V VIN VIL (MAX) (VCCIO-0.2) VIN VCCIO VCCIO VIN 5.25V 0V VIN VIL (MAX) VIN = VIL (MAX) VIN = VIH (MIN) 0V VIN VCCIO 0V VIN VCCIO VCC = 3.3V, VOUT = 0.5V, TA = 25C VIL = 0.5V, VIH = VCC One input toggling at 50% duty cycle, outputs open. - MIN. - - - - 40 -40 - - VIL - - - TYP.2 - - - - - - - - - - 16.5 See Note 3 - MAX. -10 10 50 -200 - - 550 -550 VIH -250 - - UNITS A A A A A A A A V mA mA mA/ MHz mA IIL IIH IPU IBHLS IBHHS IBHLO IBHHO IBHT IOS1 ICCQ4 ICC ICONT 5 - 160 DC Char_gdx160va 1. One output at a time for a maximum of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized, but not 100% tested. 2. Typical values are at VCC = 3.3V and TA = 25C. 3. ICC / MHz = (0.003 x I/O cell fanout) + 0.029. e.g. An input driving four I/O cells at 40MHz results in a dynamic ICC of approximately ((0.003 x 4) + 0.029) x 40 = 1.64mA. 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. 10 Specifications ispGDX160VA External Timing Parameters Over Recommended Operating Conditions TEST1 PARAMETER COND. # -3 DESCRIPTION - - 250 1 tsu3+tgco1 -5 3.5 3.5 - - - - - - - - - - - - - - - - 3.5 6.0 4.0 7.0 5.0 5.0 6.0 6.0 - - 8.0 - 3.5 - - 143 111 4.0 3.0 4.0 3.0 2.5 1.5 4.5 0.0 1.5 0.0 1.5 0.0 1.5 0.0 - - - - - - - - 3.5 3.5 - 10.0 - 5.0 5.0 - - - - - - - - - - - - - - - - 5.0 8.5 6.0 9.5 6.0 6.0 6.0 6.0 - - 14.0 - 5.0 UNITS ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN. MAX. MIN. MAX. ns 0.5 - 0.5 - A 32 Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except tsl. 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. tpd2 tsel2 fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco12 tgco22 tco12 tco22 ten2 tdis2 ttoeen2 ttoedis2 twh twl trst trw tsl tsk A A - - - - - - - - - - - - - - - - A A A A B C B C - - - - D 1 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX) 2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) 3 Clock Frequency, Max. Toggle 4 Clock Frequency with External Feedback ( ) 166.7 3.0 2.5 2.5 2.0 2.5 1.5 3.0 0.0 0.5 0.0 1.0 0.0 1.0 0.0 - - - - - - - - 2.0 2.0 - 5.0 - 5 Input Latch or Register Setup Time Before Yx 6 Input Latch or Register Setup Time Before I/O Clock 7 Output Latch or Register Setup Time Before Yx 8 Output Latch or Register Setup Time Before I/O Clock 9 Global Clock Enable Setup Time Before Yx 10 Global Clock Enable Setup Time Before I/O Clock 11 I/O Clock Enable Setup Time Before Yx 12 Input Latch or Reg. Hold Time (Yx) 13 Input Latch or Reg. Hold Time (I/O Clock) 14 Output Latch or Reg. Hold Time (Yx) 15 Output Latch or Reg. Hold Time (I/O Clock) 16 Global Clock Enable Hold Time (Yx) 17 Global Clock Enable Hold Time (I/O Clock) 18 I/O Clock Enable Hold Time (Yx) 19 Output Latch or Reg. Clock (from Yx) to Output Delay 20 Input Latch or Register Clock (from Yx) to Output Delay 21 Output Latch or Register Clock (from I/O pin) to Output Delay 22 Input Latch or Register Clock (from I/O pin) to Output Delay 23 Input to Output Enable 24 Input to Output Disable 25 Test OE Output Enable 26 Test OE Output Disable 27 Clock Pulse Duration, High 28 Clock Pulse Duration, Low 29 Register Reset Delay from RESET Low 30 Reset Pulse Width 31 Output Delay Adder for Output Timings Using Slow Slew Rate 11 Specifications ispGDX160VA External Timing Parameters Over Recommended Operating Conditions TEST1 PARAMETER COND. # -7 DESCRIPTION - - 100 1 tsu3+tgco1 -9 7.0 7.0 - - - - - - - - - - - - - - - - 7.0 11.0 9.0 13.0 8.5 8.5 8.5 8.5 - - 18.0 - 7.0 - - 83 62.5 7.0 6.0 7.0 6.0 4.0 3.0 8.5 0.0 3.0 0.0 3.0 0.0 3.0 0.0 - - - - - - - - 6.0 6.0 - 18.0 - 9.0 9.0 - - - - - - - - - - - - - - - - 9.0 13.5 11.5 15.7 10.5 10.5 10.5 10.5 - - 22.0 - 9.0 UNITS ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN. MAX. MIN. MAX. ns 1.0 - A 32 Output Skew (tgco1 Across Chip) - 0.5 1. All timings measured with one output switching, fast output slew rate setting, except tsl. 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. tpd2 tsel2 fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco12 tgco22 tco12 tco22 ten2 tdis2 ttoeen2 ttoedis2 twh twl trst trw tsl tsk A A - - - - - - - - - - - - - - - - A A A A B C B C - - - - D 1 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX) 2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) 3 Clock Frequency, Max. Toggle 4 Clock Frequency with External Feedback ( ) 80 5.5 4.5 5.5 4.5 3.5 2.5 6.5 0.0 2.5 0.0 2.5 0.0 2.5 0.0 - - - - - - - - 5.0 5.0 - 14.0 - 5 Input Latch or Register Setup Time Before Yx 6 Input Latch or Register Setup Time Before I/O Clock 7 Output Latch or Register Setup Time Before Yx 8 Output Latch or Register Setup Time Before I/O Clock 9 Global Clock Enable Setup Time Before Yx 10 Global Clock Enable Setup Time Before I/O Clock 11 I/O Clock Enable Setup Time Before Yx 12 Input Latch or Reg. Hold Time (Yx) 13 Input Latch or Reg. Hold Time (I/O Clock) 14 Output Latch or Reg. Hold Time (Yx) 15 Output Latch or Reg. Hold Time (I/O Clock) 16 Global Clock Enable Hold Time (Yx) 17 Global Clock Enable Hold Time (I/O Clock) 18 I/O Clock Enable Hold Time (Yx) 19 Output Latch or Reg. Clock (from Yx) to Output Delay 20 Input Latch or Register Clock (from Yx) to Output Delay 21 Output Latch or Register Clock (from I/O pin) to Output Delay 22 Input Latch or Register Clock (from I/O pin) to Output Delay 23 Input to Output Enable 24 Input to Output Disable 25 Test OE Output Enable 26 Test OE Output Disable 27 Clock Pulse Duration, High 28 Clock Pulse Duration, Low 29 Register Reset Delay from RESET Low 30 Reset Pulse Width 31 Output Delay Adder for Output Timings Using Slow Slew Rate 12 Specifications ispGDX160VA External Timing Parameters (Continued) ispGDX160VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the GRP Delay with increased GRP loads. These deltas apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder. ispGDX160VA Maximum GRP Delay vs. I/O Cell Fanout 1.6 GRP Delay (ns) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 4 10 20 30 40 50 I/O Cell Fanout 60 70 13 Specifications ispGDX160VA Internal Timing Parameters1 Over Recommended Operating Conditions -3 PARAMETER Inputs tio GRP tgrp MUX tmuxd tmuxexp tmuxs tmuxsio tmuxsg tmuxselexp Register tiolat tiosu tioh tioco tior tcesu tceh Data Path tfdbk tiobp tioob tmuxcg tmuxcio tiodg tiodio Outputs tob tobs toeen toedis tgoe ttoe Clocks tioclk tgclk tgclkeng tgclkenio tioclkeng Global Reset tgr 65 Global Reset to I/O Register Latch -- 6.0 -- 11.0 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Input Buffer Delay GRP Delay I/O Cell MUX A/B/C/D Data Delay I/O Cell MUX A/B/C/D Expander Delay I/O Cell Data Select I/O Cell Data Select (I/O Clock) I/O Cell Data Select (Yx Clock) I/O Cell MUX Data Select Expander Delay I/O Latch Delay I/O Register Setup Time Before Clock I/O Register Hold Time After Clock I/O Register Clock to Output Delay I/O Reset to Output Delay I/O Clock Enable Setup Time Before Clock I/O Clock Enable Hold Time After Clock I/O Register Feedback Delay I/O Register Bypass Delay I/O Register Output Buffer Delay I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) I/O Register I/O MUX Delay (Yx Clock) I/O Register I/O MUX Delay (I/O Clock) Output Buffer Delay Output Buffer Delay (Slow Slew Option) I/O Cell OE to Output Enable I/O Cell OE to Output Disable GRP Output Enable and Disable Delay Test OE Enable and Disable Delay I/O Clock Delay Global Clock Delay Global Clock Enable (Yx Clock) Global Clock Enable (I/O Clock) I/O Clock Enable (Yx Clock) DESCRIPTION1 -5 MIN. MAX. MIN. MAX. UNITS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.4 1.1 1.0 1.5 1.0 1.5 1.5 1.5 1.0 0.8 1.7 1.2 1.0 2.3 0.2 0.6 0.0 0.0 1.5 1.5 3.5 3.5 1.0 4.5 3.5 3.5 0.0 2.5 0.3 1.3 1.5 1.0 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.9 1.1 1.5 2.0 1.5 3.0 2.0 2.0 1.0 2.0 1.5 0.5 1.5 2.0 0.5 0.9 0.0 0.0 2.0 3.0 4.0 5.0 1.5 6.5 4.0 4.0 0.0 2.0 2.0 2.0 2.5 3.5 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 14 Specifications ispGDX160VA Internal Timing Parameters1 Over Recommended Operating Conditions -7 PARAMETER Inputs tio GRP tgrp MUX tmuxd tmuxexp tmuxs tmuxsio tmuxsg tmuxselexp Register tiolat tiosu tioh tioco tior tcesu tceh Data Path tfdbk tiobp tioob tmuxcg tmuxcio tiodg tiodio Outputs tob tobs toeen toedis tgoe ttoe Clocks tioclk tgclk tgclkeng tgclkenio tioclkeng Global Reset tgr 65 Global Reset to I/O Register Latch -- 13.7 -- 16.4 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Input Buffer Delay GRP Delay I/O Cell MUX A/B/C/D Data Delay I/O Cell MUX A/B/C/D Expander Delay I/O Cell Data Select I/O Cell Data Select (I/O Clock) I/O Cell Data Select (Yx Clock) I/O Cell MUX Data Select Expander Delay I/O Latch Delay I/O Register Setup Time Before Clock I/O Register Hold Time After Clock I/O Register Clock to Output Delay I/O Reset to Output Delay I/O Clock Enable Setup Time Before Clock I/O Clock Enable Hold Time After Clock I/O Register Feedback Delay I/O Register Bypass Delay I/O Register Output Buffer Delay I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) I/O Register I/O MUX Delay (Yx Clock) I/O Register I/O MUX Delay (I/O Clock) Output Buffer Delay Output Buffer Delay (Slow Slew Option) I/O Cell OE to Output Enable I/O Cell OE to Output Disable GRP Output Enable and Disable Delay Test OE Enable and Disable Delay I/O Clock Delay Global Clock Delay Global Clock Enable (Yx Clock) Global Clock Enable (I/O Clock) I/O Clock Enable (Yx Clock) DESCRIPTION1 -9 MIN. MAX. MIN. MAX. UNITS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.4 1.1 2.0 2.5 2.0 4.5 2.5 2.5 1.0 3.2 2.3 0.5 1.5 2.5 1.0 1.2 0.3 0.6 2.5 4.5 5.0 7.0 2.2 9.2 6.0 6.0 0.0 2.5 3.2 2.7 3.7 5.7 4.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.9 1.1 2.5 3.0 2.5 6.0 3.0 3.0 1.0 4.4 2.6 0.5 1.5 2.0 2.0 1.3 0.6 0.7 3.0 6.0 6.0 9.0 2.9 11.9 7.5 7.5 0.0 3.0 4.4 3.4 5.4 8.4 6.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 Specifications ispGDX160V Absolute Maximum Ratings 1,2 Supply Voltage Vcc ................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C 1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Conditions SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial TA = 0C to +70C TA = -40C to +85C MIN. 3.0 3.0 -0.3 2.0 MAX. 3.6 3.6 0.8 5.25 UNITS V V V V Table 2-0005/gdxv VCC VIL VIH1 1 1. Typical 100mV of input hysteresis. Capacitance (TA=25oC, f=1.0 MHz) SYMBOL PARAMETER I/O Capacitance Dedicated Clock Capacitance TYPICAL 8 10 UNITS pf pf TEST CONDITIONS VCC = 3.3V, VI/O = 2.0V VCC = 3.3V, VY = 2.0V Table 2 - 0006 C1 C2 Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM -- UNITS Cycles 16 Specifications ispGDX160V Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 1.5ns 10% to 90% 1.5V 1.5V See figure at right + 3.3V R1 Device Output R2 CL * Test Point 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V Slow Slew R1 153 R2 134 134 CL 35pF 35pF 35pF 5pF 5pF 35pF Table 2-0004A *CL includes Test Fixture and Probe Capacitance. 153 134 153 C D DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pull-Up Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points Output Short Circuit Current Quiescent Power Supply Current Dynamic Power Supply Current per Input Switching Maximum Continuous I/O Pin Sink Current Through Any GND Pin VCC = 3.3V, VOUT = 0.5V, TA = 25C VIL = 0.5V, VIH = VCC One input toggling @ 50% duty cycle, outputs open. IOL =24 mA IOH =-12 mA 0V VIN VIL (Max.) VCC VIN 5.25V 0V VIN VIL VIN = VIL (Max.) VIN = VIH (Min.) 0V VIN VCC 0V VIN VCC CONDITION MIN. - 2.4 - - - 50 -50 - - VIL - - - - TYP.2 - - - - - - - - - - - 70 See Note 3 MAX. 0.55 - -10 10 -150 - - 550 -550 VIH -250 - - 96 UNITS V V A A A A A A A V mA mA mA/MHz mA VOL VOH IIL IIH IIL-PU IBHLS IBHHS IBHLO IBHHO IBHT IOS1 ICCQ4 ICC ICONT5 - 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Typical values are at VCC = 3.3V and TA = 25oC. 3. ICC / MHz = (0.01 x I/O cell fanout) + 0.04 e.g. An input driving four I/O cells at 40 MHz results in a dynamic ICC of approximately ((0.01 x 4) + 0.04) x 40 = 3.2 mA. 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bidirectionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. 17 Specifications ispGDX160V External Timing Parameters Over Recommended Operating Conditions 1 PARAMETER TEST COND. # 1 2 3 4 5 6 7 8 9 DESCRIPTION Data Prop. Delay from Any I/O pin to Any I/O pin (4:1 MUX) Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) Clock Frequency, Max. Toggle Clock Frequency with External Feedback ( 1 tsu3+tgco1 -5 - - 143 110 4.0 3.0 4.0 3.0 2.5 1.5 4.5 0.0 1.5 0.0 1.5 0.0 1.5 0.0 - - - - - - - - 3.5 3.5 - 10.0 - - 5.0 6.5 - - - - - - - - - - - - - - - - 5.0 8.5 6.0 9.5 6.0 6.0 9.0 9.0 - - 14.0 - 8.0 0.5 - - 100 -7 7.0 9.0 - - - - - - - - - - - - - - - - 7.0 11.0 9.0 13.0 8.5 8.5 12.0 12.0 - - 18.0 - 12.0 0.5 UNITS ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN. MAX. MIN. MAX. 32 Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except tsl. tpd tsel fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco1 tgco2 tco1 tco2 ten tdis ttoeen ttoedis twh twl trst trw tsl tsk A A - - - - - - - - - - - - - - - - A A A A B C B C - - - - D A ) 80.0 5.5 4.5 5.5 4.5 3.5 2.5 6.5 0.0 2.5 0.0 2.5 0.0 2.5 0.0 - - - - - - - - 5.0 5.0 - 14.0 - - Input Latch or Register Setup Time Before Yx Input Latch or Register Setup Time Before I/O Clock Output Latch or Register Setup Time Before Yx Output Latch or Register Setup Time Before I/O Clock Global Clock Enable Setup Time Before Yx 10 Global Clock Enable Setup Time Before I/O Clock 11 I/O Clock Enable Setup Time Before Yx 12 Input Latch or Register Hold Time (Yx) 13 Input Latch or Register Hold Time (I/O Clock) 14 Output Latch or Register Hold Time (Yx) 15 Output Latch or Register Hold Time (I/O Clock) 16 Global Clock Enable Hold Time (Yx) 17 Global Clock Enable Hold Time (I/O Clock) 18 I/O Clock Enable Hold Time (Yx) 19 Output Latch or Register Clock (from Yx) to Output Delay 20 Input Latch or Register Clock (from Yx) to Output Delay 21 Output Latch or Register Clock (from I/O pin) to Output Delay 22 Input Latch or Register Clock (from I/O pin) to Output Delay 23 Input to Output Enable 24 Input to Output Disable 25 Test OE Output Enable 26 Test OE Output Disable 27 Clock Pulse Duration, High 28 Clock Pulse Duration, Low 29 Register Reset Delay from RESET Low 30 Reset Pulse Width 31 Output Delay Adder for Output Timings Using Slow Slew Rate 18 Specifications ispGDX160V External Timing Parameters (Continued) ispGDX160V timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the GRP Delay with increased GRP loads. These deltas apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder. ispGDX160V Maximum GRP Delay vs. I/O Cell Fanout 10 GRP Delay (ns) 8 6 4 2 0 4 10 20 30 40 50 60 70 I/O Cell Fanout 19 Specifications ispGDX160V Internal Timing Parameters1 Over Recommended Operating Conditions -5 PARAMETER Inputs tio GRP tgrp MUX tmuxd tmuxexp tmuxs tmuxsio tmuxsg tmuxselexp Register tiolat tiosu tioh tioco tior tcesu tceh Data Path tfdbk tiobp tioob tmuxcg tmuxcio tiodg tiodio Outputs tob tobs toeen toedis tgoe ttoe Clocks tioclk tgclk tgclkeng tgclkenio tioclkeng Global Reset tgr 65 Global Reset to I/O Register Latch -- 11.0 -- 13.7 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Input Buffer Delay GRP Delay I/O Cell MUX A/B/C/D Data Delay I/O Cell MUX A/B/C/D Expander Delay I/O Cell Data Select I/O Cell Data Select (I/O Clk) I/O Cell Data Select (Yx Clk) I/O Cell MUX Data Select Expander Delay I/O Latch Delay I/O Register Setup Time Before Clock I/O Register Hold Time After Clock I/O Register Clock to Output Delay I/O Reset to Output Delay I/O Clock Enable Setup Time Before Clock I/O Clock Enable Hold Time After Clock I/O Register Feedback Delay I/O Register Bypass Delay I/O Register Output Buffer Delay I/O Register A/B/C/D Data Input MUX Delay (Yx Clk) I/O Register A/B/C/D Data Input MUX Delay (I/O Clk) I/O Register I/O MUX Delay (Yx Clk) I/O Register I/O MUX Delay (I/O Clk) Output Buffer Delay Output Buffer Delay (Slow Slew Option) I/O Cell OE to Output Enable I/O Cell OE to Output Disable GRP Output Enable and Disable Delay Test OE Enable and Disable Delay I/O Clock Delay Global Clock Delay Global Clock Enable (Yx Clk) Global Clock Enable (I/O Clk) I/O Clock Enable (Yx Clk) DESCRIPTION1 -7 MIN. MAX. MIN. MAX. UNITS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.9 1.1 1.5 2.0 3.0 4.5 3.5 3.5 1.0 2.0 1.5 0.5 1.5 2.0 0.5 0.9 0.0 0.0 2.0 3.0 4.0 5.0 1.5 9.5 4.0 4.0 0.0 5.0 2.0 2.0 2.5 3.5 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.4 1.1 2.0 2.5 4.0 6.5 4.5 4.5 1.0 3.2 2.3 0.5 1.5 2.5 1.0 1.2 0.3 0.6 2.5 4.5 5.0 7.0 2.2 14.2 6.0 6.0 0.0 6.0 3.2 2.7 3.7 5.7 4.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 Specifications ispGDX160V/VA Switching Waveforms MUXSEL (I/O INPUT) VALID INPUT DATA (I/O INPUT) VALID INPUT tsel DATA (I/O INPUT) VALID INPUT tsu CLK th tgco tco tpd COMBINATORIAL I/O OUTPUT REGISTERED I/O OUTPUT Combinatorial Output 1/fmax (external fdbk) tsuce OE (I/O INPUT) CLKEN tceh tdis COMBINATORIAL I/O OUTPUT ten Registered Output I/O Output Enable/Disable RESET trw twh CLK (I/O INPUT) twl REGISTERED I/O OUTPUT trst Clock Width Reset ispGDXV Timing Model OE tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 tmuxcg #50 tmuxcio #51 tgoe #58 MUX Expander Input A B C D MUX0 GRP MUX1 tmuxexp #35 tmuxselexp #39 MUX Expander Output TOE ttoe #59 tiobp #48 D CLKEN CLK Q tioob #49 tob #54 tobs #55 toeen #56 toedis #57 I/O Pin tgrp #33 tiod #52, #53 tiolat #40 tiosu #41 tioh #42 tioco #43 tior #44 tcesu #45 tceh #46 tgr #65 RESET tfdbk #47 tio #32 CLKEN CLK tioclkeg #64 tioclk #60 Y0,1,2,3 tgclk #61 Y0,1,2,3, Enable 0902/gdx160v/va tgclkeng #62 tgclkenio #63 21 Specifications ispGDX160V/VA ispGDX Development System The ispGDX Development System supports ispGDX design using a simple language syntax and an easy-touse Graphical User Interface (GUI) called Design Manager. From creation to In-System Programming, the ispGDX system is an easy-to-use, self-contained design tool delivered on CD-ROM media. Status Bar and the work area. The figure below shows these elements of the ispGDX GUI. The Menu Bar displays topics related to functions used in the design process. Access the various drop-down menus and submenus by using the mouse or "hot" keys. The menu items available in the ispGDX system are FILE, EDIT, DEVICE, INVOKE, INTERFACES, VIEW, WINDOW and HELP. The Tool Bar is a quick and easy way to perform many of the functions found in the menus with a single click of the mouse. File, Edit, Undo, Redo, Find, Print Download and Compiler are just some of the Icons found in the ispGDX Tool Bar. For instance, the Compiler Icon performs the same function as the Invoke => Compiler menu commands, including design analysis and rule checking and the fitting operation. The Status Bar displays action prompts and the line and column numbers reflect the location of the cursor within the message window or the work area. Features * Easy-to-use Text Entry System * ispGDX Design Compiler - Design Rule Checker - I/O Connectivity Checker - Automatic Compiler Function * Industry Standard JEDEC File for Programming * Min / Max Timing Report * Interfaces To Popular Timing Simulators * User Electronic Signature (UES) Support * Detailed Log and Report Files For Easy Design Debug * On-Line Help * Windows(R) 3.1x, Windows 95, Windows 98 and Windows NT(R) Compatible Graphical User Interface * SUN O/S, Command Line Driven version available Workstation Version The ispGDX software is also available for use under the Sun O/S 4.1.x or Solaris 2.4 or 2.5. The Sun version of the ispGDX software is invoked from the command line under the UNIX operating system. A GUI is not supported in this environment. In the UNIX environment, the ispGDX Design File (GDF) must be created using a text editor. Once the GDF has been created, invoke the ispGDX workstation software from the UNIX command line. The following is an example of how to invoke ispGDX software. Usage: ispGDX [-i input_file] [-of[edif|orcad|viewlogic|verilog|vhdl]] [-p part name] [-r par_file] Where: -i input_file -of [edif | orcad | viewlogic | verilog | vhdl] -p part_name -r par_file ispGDX design file Output format ispGDX part number Read parameters from parameter file PC Version With the ispGDX GUI for the PC, command line entry is not required. The tools run under Microsoft Windows 3.1, Windows 95, Windows 98 and Windows NT. When the ispGDX software is invoked, the Design Manager and an accompanying message window are displayed. The Design Manager consists of the Menu Bar, Tool Bar, Lattice's ispGDX Development System Interface 22 Specifications ispGDX160V/VA ispGDX Development System (Continued) The GDF File The GDF file is a simple text description of the design function, device and pin parameters. The file has four parts: device selection, set and constant statements, a pin section and a connection section. A sample file looks like this: // 32-Bit Data 3 to 1 Mux DESIGN datamux; This example shows a simple, but complete, 32-bit 3:1 MUX design. Once completed, the compiler takes over. Powerful Syntax Lattice's ispGDX Design System uses simple, but powerful, syntax to easily define a design. The !(bang) operator controls pin polarity and can be used in both the pin and connection sections of the design definition. Dot extensions define data inputs, select controls for the 4:1 multiplexor, and control inputs of sequential elements and tri-state buffers. Dot extensions are .M# (MUX Input), .S# (MUX Select), and control functions, such as .CLK, .EN, .OE and .A (shown in adjacent table). Pin Attributes are assigned in the pin section of the GDF as well. SLOWSLEW selects the slow slew rate for an output buffer. The Pull parameter can be used to select the internal pull-up or bus hold latch. OPEN drain can be used to select open drain operation. The COMB attribute distinguishes the structure for bidirectional pins. If COMB is used, the input register, or latch, of an output buffer will be applied to bidirectional pins. Please consult the ispGDX Development System Manual for full details. ispGDX GDF File Dot Extensions Type Dot Ext. .M0 MUX Input .M1 .M2 .M3 .S0 .S1 .CLK .EN Description MUXA Data input to 4:1 MUX MUXB Data input to 4:1 MUX MUXC Data Input to 4:1 MUX MUXD Data input to 4:1 MUX MUX0 Selection input to 4:1 MUX MUX1 Selection input to 4:1 MUX Clock for a register Latch enable for a latch signal Output enable for 3-state output or bidirectional signal Clock enable for register clock Adjacent MUX output of an I/O cell ispGDXV Dot Ext PART ispGDX160V-7Q208; PARAM SECURITY ON; PARAM OPENDRAIN ON; PARAM PULL HOLD; // // // // USE OPEN DRAIN OPTION USE BUS HOLD LATCH OPTION SET SET SET SET BUS_A BUS_B BUS_C BUS_D [dataA31..dataA0]; [dataB31..dataB0]; [dataC31..dataC0]; [dataD31..dataD0]; {A31..A0}; {B31..B0}; {C31..C0}; {D31..D0}; INPUT INPUT INPUT OUTPUT BUS_A BUS_B BUS_C BUS_D INPUT [oe] {B37}; INPUT [clk] {B36}; INPUT [sel1] INPUT [sel0] BEGIN BUS_D.m0 BUS_D.m1 BUS_D.m2 BUS_D.m3 = = = = BUS_A; BUS_B; BUS_C; VCC; {B38}; {B39}; MUX Selection Control .OE .CE // Default all // outputs to VCC MUX Output .A BUS_D.s1 = sel1; BUS_D.s0 = sel0; BUS_D.oe = oe; BUS_D.clk = clk; END 23 Specifications ispGDX160V/VA ispGDX Development System (Continued) The ispGDX Design System Compiler After the GDF file is created, the compiler checks the syntax and provides helpful hints and the location of any syntax errors. The compiler performs design rule checks, such as, clock and enable designations, the use of input/ output/BIDI usage, and the proper use of attributes. I/O connectivity is also checked to ensure polarity, MUX selection controls, and connections are properly made. Compilation is completed automatically and report and programming files are saved. Third-Party Timing Simulation The ispGDX Design System will generate simulation netlists as specified by a user. The simulation netlist formats available are: EDIF, Verilog (OVI compliant), VHDL (VITAL compliant), Viewlogic, and OrCAD. For In-System Programming, Lattice's ispGDX devices may be programmed, alone or in a chain with up to 100 other Lattice ISP devices, using Lattice's ISP Daisy Chain Download software. This powerful Windows-based tool can be launched from the Tool Bar or by Invoking the Download option from the drop down menu within the ispGDX Design System. ISP Daisy Chain Download version 7.1 or above supports the ispGDX Family devices. Reports Generated When the ispGDX system compiles a design and generates the specified netlists, the following output files are created: Report Files: .log Compiler History .rpt Compiler Report .mfr Maximum Frequency Timing Report .tsu Set-up and Hold Timing Report .tco Clock to Out Timing Report .tpt Timing Report Simulation File: .sim Post-Route Simulation With LAC Format Netlists: .edo .vlo .ifo .vho .vhn .vto EDIF Output Verilog Output OrCAD Output VHDL non-VITAL with Maximum Delays Output VHDL non-VITAL with Maximum Delays Output VHDL VITAL Output Download: .jed JEDEC Device Programming File 24 Specifications ispGDX160V/VA In-System Programmability All necessary programming of the ispGDXV/VA is done via four TTL level logic interface signals. These four signals are fed into the on-chip programming circuitry where a state machine controls the programming. On-chip programming can be accomplished using an IEEE 1149.1 boundary scan protocol. The IEEE 1149.1compliant interface signals are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS) control. The EPEN pin is also used to enable or disable the JTAG port. The embedded controller port enable pin (EPEN) is used to enable the JTAG tap controller and in that regard has similar functionality to a TRST pin. When the pin is driven high, the JTAG TAP controller is enabled. This is also true Figure 9. ispJTAG Device Programming Interface TDO TDI TMS TCK EPEN ispJTAG Programming Interface when the pin is left unconnected, in which case the pin is pulled high by the permanent internal pullup. This allows ISP programming and BSCAN testing to take place as specified by the Instruction Table. When the pin is driven low, the JTAG TAP controller is driven to a reset state asynchronously. It stays there while the pin is held low. After pulling the pin high the JTAG controller becomes active. The intent of this feature is to allow the JTAG interface to be directly controlled by the data bus of an embedded controller (hence the name Embedded Port Enable). The EPEN signal is used as a "device select" to prevent spurious programming and/or testing from occuring due to random bit patterns on the data bus. Figure 9 illustrates the block diagram for the ispJTAG interface. ispGDX 160V/VA Device ispLSI Device ispMACH Device ispGDX 160V/VA Device ispGDX 160V/VA Device 25 Specifications ispGDX160V/VA Boundary Scan The ispGDXV/VA devices provide IEEE1149.1a test capability and ISP programming through a standard Boundary Scan Test Access Port (TAP) interface. The boundary scan circuitry on the ispGDXV/VA Family operates independently of the programmed pattern. This Figure 10. Boundary Scan Register Circuit for I/O Pins HIGHZ allows customers using boundary scan test to have full test capability with only a single BSDL file. The ispGDXV/VA devices are identified by the 32-bit JTAG IDCODE register. The device ID assignments are listed in Table 4. EXTEST SCANIN (from previous cell BSCAN Registers BSCAN Latches TOE Normal Function OE 0 1 D Q D Q EXTEST PROG_MODE Normal Function 0 I/O Pin 1 D Q D Q D Q SCANOUT (to next cell) Shift DR Clock DR Update DR Reset Table 3. I/O Shift Register Order DEVICE ispGDX160V/VA I/O SHIFT REGISTER ORDER TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B20 .. B39, I/O C0 .. C39, I/O D0 .. D19, I/O B19 .. B0, I/O A39.. A0, I/O D39 .. D20, TDO I/O Shift Reg Order/ispGDXVA Table 4. ispGDX160V/VA Device ID Codes DEVICE ispGDX160V ispGDX160VA 32-BIT BOUNDARY SCAN ID CODE 0000, 0000, 0011, 0101, 0011, 0000, 0100, 0011 0001, 0000, 0011, 0101, 0011, 0000, 0100, 0011 ID Code/GDX160V/VA 26 Specifications ispGDX160V/VA Boundary Scan (Continued) The ispJTAG programming is accomplished by executing Lattice private instructions under the Boundary Scan State Machine. Details of the programming sequence are transparent to the user and are handled by Lattice ISP Daisy Chain Figure 11. Boundary Scan Register Circuit for Input-Only Pins Downlowad (ispDCDTM), ispCODE `C' routines or any third-party programmers. Contact Lattice Technical Support to obtain more detailed programming information. Input Pin SCANIN (from previous cell Shift DR Clock DR D Q SCANOUT (to next cell) Figure 12. Boundary Scan State Machine 1 Test-Logic-Reset 0 1 Run-Test/Idle 0 Select-DR-Scan 0 1 Capture-DR 0 Shift-DR 0 1 Exit1-DR 1 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 1 1 Select-IR-Scan 0 1 Capture-IR 0 Shift-IR 0 1 Exit1-IR 1 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0 27 Specifications ispGDX160V/VA Boundary Scan (Continued) Figure 13. Boundary Scan Waveforms and Timing Specifications TMS TDI Tbtsu Tbtch TCK Tbtcl Tbth Tbtcp Tbtvo TDO Valid Data Tbtco Valid Data Tbtoz Tbtcsu Data to be captured Tbtch Data Captured Tbtuov Data to be driven out Tbtuco Valid Data Tbtuoz Valid Data Symbol tbtcp tbtch tbtcl tbtsu tbth trf tbtco tbtoz tbtvo tbtcpsu tbtcph tbtuco tbtuoz tbtuov Parameter TCK [BSCAN test] clock pulse width TCK [BSCAN test] pulse width high TCK [BSCAN test] pulse width low TCK [BSCAN test] setup time TCK [BSCAN test] hold time TCK [BSCAN test] rise and fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to data output disable TAP controller falling edge of clock to data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge of clock to valid output BSCAN test Update reg, falling edge of clock to output disable BSCAN test Update reg, falling edge of clock to output enable Min 100 50 50 20 25 50 - - - 20 25 - - - Max - - - - - - 25 25 25 - - 50 50 50 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns 28 Specifications ispGDX160V/VA Signal Descriptions Signal Name I/O Description Input/Output Pins - These are the general purpose bidirectional data pins. When used as outputs, each may be independently latched, registered or tristated. They can also each assume one other control function (OE, CLK/CLKEN, and MUXsel as described in the text). Test Output Enable Pin - This pin tristates all I/P pins when a logic low is driven. Active LOW Input Pin - Resets all I/O register outputs when LOW. Input Pins -These can be either Global Clocks or Clock Enables. Input Pin - JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low, JTAG TAP controller is driven to reset. Input Pin - Serial data input during ISP programming or Boundary Scan mode. Input Pin - Serial data clock during ISP programming or Boundary Scan mode. Input Pin - Control input during ISP programming or Boundary Scan mode. Output Pin - Serial data output during ISP programming or Boundary Scan mode. Ground (GND) Vcc - Supply voltage (3.3V). Input - This pin is used if optional 2.5V output is to be used. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply. No Connect. TOE RESET Yx/CLKENx EPEN TDI TCK TMS TDO GND VCC VCCIO2 NC1 1. NC pins are not to be connected to any active signals, VCC or GND. 2. "VA" version only. 29 Specifications ispGDX160V/VA Signal Locations: ispGDX160V/VA Signal TOE RESET Y0/CLKEN0 Y1/CLKEN1 Y2/CLKEN2 Y3/CLKEN3 EPEN TDI TCK TMS TDO GND 178 185 75 76 180 181 183 81 80 79 78 6, 15, 25, 35, 44, 54, 63, 77, 91, 100, 110, 119, 129, 139, 148, 159, 168, 182, 195, 204 1, 17, 33, 49, 65, 89, 105, 121, 137, 153, 1561, 170, 184, 193 1561 73, 74, 179 208-Pin PQFP D9 A8 N8 R8 B9 C9 A9 P9 T9 T8 P8 208-Ball fpBGA A12 D10 V10 Y10 C11 A11 B10 Y12 U11 V11 W11 272-Ball BGA D4, D13, G7, G8, G9, A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12, G10, H7, H8, H9, H10, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, J7, J8, J9, J10, K7, K8, M11, M12, N4, N17, U4, U8, U13, U17 K9, K10, N4, N13 E131, F4, F13, L4, L13, C181, D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, M4, M13, N5, N11, N12 U10, U15 D5, D6, D12, E4 E131 A10, P7, T7 C181 A2, A6, A7, A10, A15, A19, A20, B1, B2, B4, B11, B14, B18, B19, B20, C2, C3, C10, D2, D3, D16, E2, E17, E19, H1, H3, H18, H20, K20, L1, N1, N3, N18 N20, T2, T4, T19, U5, U18, U19, V3, V14, V18, V19, W1, W2, W3, W7, W10, W14, W19, W20, Y1, Y2, Y6, Y9, Y11, Y18, Y20 VCC VCCIO NC 1. VCC on ispGDX160V, VCCIO on ispGDX160VA. 30 Specifications ispGDX160V/VA I/O Locations: ispGDX160V/VA (Ordered by I/O Signal Name and 208-Pin PQFP Location) I/O Signal VCC I/O A0 I/O A1 I/O A2 I/O A3 GND I/O A4 I/O A5 I/O A6 I/O A7 I/O A8 I/O A9 I/O A10 I/O A11 GND I/O A12 VCC I/O A13 I/O A14 I/O A15 I/O A16 I/O A17 I/O A18 I/O A19 GND I/O A20 I/O A21 I/O A22 I/O A23 I/O A24 I/O A25 I/O A26 VCC I/O A27 GND I/O A28 I/O A29 I/O A30 I/O A31 I/O A32 I/O A33 I/O A34 I/O A35 GND I/O A36 I/O A37 I/O A38 I/O A39 VCC I/O B0 I/O B1 I/O B2 I/O B3 GND I/O B4 I/O B5 I/O B6 I/O B7 I/O B8 I/O B9 I/O B10 I/O B11 GND I/O B12 VCC Control Signal CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN I/O 208 208 272 PQFP fpBGA BGA Signal 2 3 4 5 7 8 9 10 11 12 13 14 16 18 19 20 21 22 23 24 26 27 28 29 30 31 32 34 36 37 38 39 40 41 42 43 45 46 47 48 50 51 52 53 55 56 57 58 59 60 61 62 64 B2 B1 C2 A1 C1 D3 D2 D1 E3 E2 E1 F3 F2 F1 G4 G2 G3 G1 H4 H2 H3 H1 J1 J3 J2 J4 K1 K3 K2 K4 L1 L2 L3 M1 M2 M3 N1 N2 N3 P1 P2 R1 R2 T1 P3 T2 R3 P4 T3 R4 T4 P5 R5 E4 C1 D1 E3 E1 F3 G4 F2 F1 G3 G2 G1 H2 J4 J3 J2 J1 K2 K3 K1 L2 L3 L4 M1 M2 M3 M4 N2 P1 P2 R1 P3 R2 T1 P4 R3 U1 T3 U2 V1 U3 V2 W4 V4 Y3 Y4 V5 W5 Y5 V6 U7 W6 V7 I/O B13 I/O B14 I/O B15 I/O B16 I/O B17 I/O B18 I/O B19 GND I/O B20 I/O B21 I/O B22 I/O B23 I/O B24 I/O B25 I/O B26 VCC I/O B27 GND I/O B28 I/O B29 I/O B30 I/O B31 I/O B32 I/O B33 I/O B34 I/O B35 GND I/O B36 I/O B37 I/O B38 I/O B39 VCC I/O C0 I/O C1 I/O C2 I/O C3 GND I/O C4 I/O C5 I/O C6 I/O C7 I/O C8 I/O C9 I/O C10 I/O C11 GND I/O C12 VCC I/O C13 I/O C14 I/O C15 I/O C16 I/O C17 I/O C18 I/O C19 GND I/O C20 I/O C21 I/O C22 I/O C23 I/O C24 I/O C25 I/O C26 VCC I/O C27 1VCC Control Signal OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 208 208 272 I/O PQFP fpBGA BGA Signal 66 67 68 69 70 71 72 82 83 84 85 86 87 88 90 92 93 94 95 96 97 98 99 101 102 103 104 106 107 108 109 111 112 113 114 115 116 117 118 120 122 123 124 125 126 127 128 130 131 132 133 134 135 136 138 N6 T5 R6 P6 T6 N7 R7 R9 N9 T10 P10 R10 N10 T11 P11 R11 T12 P12 R12 T13 R13 T14 P13 R14 T15 T16 R15 P14 P15 R16 N14 P16 N15 N16 M14 M15 M16 L15 L14 L16 K13 K15 K14 K16 J13 J15 J14 J16 H14 H16 H15 H13 G16 G14 G15 Y7 V8 W8 Y8 U9 V9 W9 W12 V12 U12 Y13 W13 V13 Y14 Y15 W15 Y16 U14 V15 W16 Y17 V16 W17 U16 V17 W18 Y19 T17 V20 U20 T18 T20 R18 P17 R19 R20 P18 P19 P20 N19 M17 M18 M19 M20 L19 L18 L20 K19 K18 K17 J20 J19 J18 J17 H19 Control Signal 208 208 272 PQFP fpBGA BGA 140 141 142 143 144 145 146 147 149 150 151 152 154 155 157 158 160 161 162 163 164 165 166 167 169 171 172 173 174 175 176 177 G13 F16 F14 F15 E16 E14 E15 D16 C16 D15 D14 C15 B16 A16 B15 A15 C14 B14 A14 C13 B13 A13 C12 B12 D11 A12 C11 B11 D10 A11 B10 C10 G20 G19 F20 G18 F19 E20 G17 F18 D20 E18 D19 C20 D18 C19 B17 C17 A18 A17 C16 B16 A16 C15 D14 B15 C14 A14 C13 B13 A13 D12 C12 B12 GND I/O C28 CLK/CLKEN I/O C29 OE I/O C30 MUXsel1 I/O C31 MUXsel2 I/O C32 CLK/CLKEN I/O C33 OE I/O C34 MUXsel1 I/O C35 MUXsel2 GND I/O C36 CLK/CLKEN I/O C37 OE I/O C38 MUXsel1 I/O C39 MUXsel2 VCC I/O D0 CLK/CLKEN I/O D1 OE VCC/VCCIO1 I/O D2 MUXsel1 I/O D3 MUXsel2 GND I/O D4 CLK/CLKEN I/O D5 OE I/O D6 MUXsel1 I/O D7 MUXsel2 I/O D8 CLK/CLKEN I/O D9 OE I/O D10 MUXsel1 I/O D11 MUXsel2 GND I/O D12 CLK/CLKEN VCC I/O D13 OE I/O D14 MUXsel1 I/O D15 MUXsel2 I/O D16 CLK/CLKEN I/O D17 OE I/O D18 MUXsel1 I/O D19 MUXsel2 GND VCC I/O D20 CLK/CLKEN I/O D21 OE I/O D22 MUXsel1 I/O D23 MUXsel2 I/O D24 CLK/CLKEN I/O D25 OE I/O D26 MUXsel1 VCC I/O D27 MUXsel2 GND I/O D28 CLK/CLKEN I/O D29 OE I/O D30 MUXsel1 I/O D31 MUXsel2 I/O D32 CLK/CLKEN I/O D33 OE I/O D34 MUXsel1 I/O D35 MUXsel2 GND I/O D36 CLK/CLKEN I/O D37 OE I/O D38 MUXsel1 I/O D39 MUXsel2 186 187 188 189 190 191 192 194 196 197 198 199 200 201 202 203 205 206 207 208 C8 B8 D8 A7 C7 B7 D7 A6 C6 B6 A5 C5 B5 A4 B4 C4 A3 C3 B3 A2 A9 B9 C9 D9 A8 B8 C8 B7 C7 B6 A5 D7 C6 B5 A4 C5 A3 D5 C4 B3 NOTE: VCC and GND Pads Shown for Reference, in ispGDX160V 31 Specifications ispGDX160V/VA I/O Locations: ispGDX160V/VA (Ordered by 208-Ball BGA Location) I/O Signal I/O A3 I/O D39 I/O D36 I/O D33 I/O D30 I/O D27 I/O D23 I/O D17 I/O D13 I/O D9 I/O D6 I/O D3 I/O D1 I/O A1 I/O A0 I/O D38 I/O D34 I/O D32 I/O D29 I/O D25 I/O D21 I/O D18 I/O D15 I/O D11 I/O D8 I/O D5 I/O D2 I/O D0 I/O A4 I/O A2 I/O D37 I/O D35 I/O D31 I/O D28 I/O D24 I/O D20 I/O D19 I/O D14 I/O D10 I/O D7 I/O D4 I/O C39 I/O C36 I/O A7 I/O A6 I/O A5 I/O D26 I/O D22 I/O D16 I/O D12 I/O C38 I/O C37 I/O C35 I/O A10 Control Signal MUXsel2 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 MUXsel2 OE OE OE MUXsel1 MUXsel2 OE OE CLK/CLKEN MUXsel1 MUXsel1 CLK/CLKEN OE OE OE MUXsel1 MUXsel2 MUXsel2 CLK/CLKEN OE MUXsel1 CLK/CLKEN CLK/CLKEN MUXsel1 OE MUXsel2 MUXsel2 CLK/CLKEN CLK/CLKEN CLK/CLKEN MUXsel2 MUXsel1 MUXsel1 MUXsel2 CLK/CLKEN MUXsel2 CLK/CLKEN MUXsel2 MUXsel1 OE MUXsel1 MUXsel1 CLK/CLKEN CLK/CLKEN MUXsel1 OE MUXsel2 MUXsel1 I/O 208 208 272 PQFP fpBGA BGA Signal 5 208 205 201 198 194 189 175 171 165 162 158 155 3 2 207 202 200 197 191 187 176 173 167 164 161 157 154 7 4 206 203 199 196 190 186 177 172 166 163 160 152 149 10 9 8 192 188 174 169 151 150 147 13 A1 A2 A3 A4 A5 A6 A7 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D7 D8 D10 D11 D14 D15 D16 E1 E3 B3 A3 B5 A5 B7 D9 D12 A14 C15 C16 C17 C19 C1 E4 C4 A4 C6 B6 B8 B9 C12 B13 B15 A16 A17 B17 D18 E1 D1 D5 C5 D7 C7 A8 A9 B12 C13 D14 B16 A18 C20 D20 F2 G4 F3 C8 C9 A13 C14 D19 E18 F18 G2 I/O A9 I/O A8 I/O C33 I/O C34 I/O C32 I/O A13 I/O A12 I/O A11 I/O C30 I/O C31 I/O C29 I/O A17 I/O A15 I/O A16 I/O A14 I/O C28 I/O C26 I/O C27 I/O C25 I/O A21 I/O A19 I/O A20 I/O A18 I/O C24 I/O C21 I/O C23 I/O C22 I/O A22 I/O A24 I/O A23 I/O A25 I/O C17 I/O C19 I/O C18 I/O C20 I/O A26 I/O A28 I/O A27 I/O A29 I/O C13 I/O C15 I/O C14 I/O C16 I/O A30 I/O A31 I/O A32 I/O C11 I/O C10 I/O C12 I/O A33 I/O A34 I/O A35 I/O C7 Control Signal OE CLK/CLK_EN OE MUXsel1 CLK/CLKEN OE CLK/CLKEN MUXsel2 MUXsel1 MUXsel2 OE OE MUXsel2 CLK/CLKEN MUXsel1 CLK/CLKEN MUXsel1 MUXsel2 OE OE MUXsel2 CLK/CLKEN MUXsel1 CLK/CLKEN OE MUXsel2 MUXsel1 MUXsel1 CLK/CLKEN MUXsel2 OE OE MUXsel2 MUXsel1 CLK/CLKEN MUXsel1 CLK/CLKEN MUXsel2 OE OE MUXsel2 MUXsel1 CLK/CLKEN MUXsel1 MUXsel2 CLK/CLKEN MUXsel2 MUXsel1 CLK/CLKEN OE MUXsel1 MUXsel2 MUXsel2 208 208 272 I/O PQFP fpBGA BGA Signal 12 11 145 146 144 18 16 14 142 143 141 22 20 21 19 140 136 138 135 27 24 26 23 134 131 133 132 28 30 29 31 126 128 127 130 32 36 34 37 122 124 123 125 38 39 40 118 117 120 41 42 43 114 E2 E3 E14 E15 E16 F1 F2 F3 F14 F15 F16 G1 G2 G3 G4 G13 G14 G15 G16 H1 H2 H3 H4 H13 H14 H15 H16 J1 J2 J3 J4 J13 J14 J15 J16 K1 K2 K3 K4 K13 K14 K15 K16 L1 L2 L3 L14 L15 L16 M1 M2 M3 M14 G3 F1 E20 G17 F19 J4 H2 G1 F20 G18 G19 K2 J2 J1 J3 G20 J17 H19 J18 L3 K1 L2 K3 J19 K18 J20 K17 L4 M2 M1 M3 L19 L20 L18 K19 M4 P1 N2 P2 M17 M19 M18 M20 R1 P3 R2 P20 P19 N19 T1 P4 R3 R19 I/O C8 I/O C9 I/O A36 I/O A37 I/O A38 I/O B13 I/O B18 I/O B21 I/O B25 I/O C3 I/O C5 I/O C6 I/O A39 I/O B0 I/O B4 I/O B7 I/O B11 I/O B16 I/O B23 I/O B27 I/O B30 I/O B35 I/O C0 I/O C1 I/O C4 I/O B1 I/O B2 I/O B6 I/O B9 I/O B12 I/O B15 I/O B19 I/O B20 I/O B24 I/O B28 I/O B31 I/O B33 I/O B36 I/O B39 I/O C2 I/O B3 I/O B5 I/O B8 I/O B10 I/O B14 I/O B17 I/O B22 I/O B26 I/O B29 I/O B32 I/O B34 I/O B37 I/O B38 Control Signal CLK OE CLK/CLKEN OE MUXsel1 OE MUXsel1 OE OE MUXsel2 OE MUXsel1 MUXsel2 CLK/CLKEN CLK/CLKEN MUXsel2 MUXsel2 CLK/CLKEN MUXsel2 MUXsel2 MUXsel1 MUXsel2 CLK/CLKEN OE CLK/CLKEN OE MUXsel1 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel2 CLK/CLKEN CLK/CLKEN CLK/CLKEN MUXsel2 OE CLK/CLKEN MUXsel2 MUXsel1 MUXsel2 OE CLK/CLKEN MUXsel1 MUXsel1 OE MUXsel1 MUXsel1 OE CLK/CLKEN MUXsel1 OE MUXsel1 208 208 272 PQFP fpBGA BGA 115 116 45 46 47 66 71 83 87 109 112 113 48 50 55 58 62 69 85 90 94 99 106 107 111 51 52 57 60 64 68 72 82 86 92 95 97 101 104 108 53 56 59 61 67 70 84 88 93 96 98 102 103 M15 M16 N1 N2 N3 N6 N7 N9 N10 N14 N15 N16 P1 P2 P3 P4 P5 P6 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T10 T11 T12 T13 T14 T15 T16 R20 P18 U1 T3 U2 Y7 V9 V12 V13 T18 R18 P17 V1 U3 Y3 W5 W6 Y8 Y13 Y15 U14 W17 T17 V20 T20 V2 W4 V5 V6 V7 W8 W9 W12 W13 W15 V15 Y17 U16 Y19 U20 V4 Y4 Y5 U7 V8 U9 U12 Y14 Y16 W16 V16 V17 W18 32 Specifications ispGDX160V/VA I/O Locations: ispGDX160V/VA (Ordered by 272-Ball BGA Location) I/O Signal I/O D36 I/O D34 I/O D30 I/O D24 I/O D20 I/O D16 I/O D13 I/O D8 I/O D5 I/O D4 I/O D39 I/O D33 I/O D29 I/O D27 I/O D25 I/O D21 I/O D19 I/O D15 I/O D11 I/O D7 I/O D2 I/O A1 I/O D38 I/O D35 I/O D32 I/O D28 I/O D26 I/O D22 I/O D18 I/O D14 I/O D12 I/O D9 I/O D6 I/O D3 I/O D1 I/O C39 I/O A2 I/O D37 I/O D31 I/O D23 I/O D17 I/O D10 I/O D0 I/O C38 I/O C36 I/O A4 I/O A3 I/O A0 I/O C37 I/O C33 I/O A8 I/O A7 I/O A5 I/O C35 Control Signal CLK/CLKEN MUXsel1 MUXsel1 CLK/CLKEN CLK/CLKEN CLK/CLKEN OE CLK/CLKEN OE CLK/CLKEN MUXsel2 OE OE MUXsel2 OE OE MUXsel2 MUXsel2 MUXsel2 MUXsel2 MUXsel1 OE MUXsel1 MUXsel2 CLK/CLKEN CLK/CLKEN MUXsel1 MUXsel1 MUXsel1 MUXsel1 CLK/CLKEN OE MUXsel1 MUXsel2 OE MUXsel2 MUXsel1 OE MUXsel2 MUXsel2 OE MUXsel1 CLK/CLKEN MUXsel1 CLK/CLKEN CLK/CLK_EN MUXsel2 CLK/CLKEN OE OE CLK/CLKEN MUXsel2 OE MUXsel2 I/O 208 208 272 PQFP fpBGA BGA Signal 205 202 198 190 186 174 171 164 161 160 208 201 197 194 191 187 177 173 167 163 157 3 207 203 200 196 192 188 176 172 169 165 162 158 155 152 4 206 199 189 175 166 154 151 149 7 5 2 150 145 11 10 8 147 A3 B4 A5 C7 C8 D10 A12 B13 B14 C14 A2 A4 B6 A6 B7 B8 C10 B11 B12 C13 B15 B1 B3 C4 B5 C6 D7 D8 B10 C11 D11 A13 A14 A15 A16 C15 C2 C3 C5 A7 A11 C12 B16 D14 C16 C1 A1 B2 D15 E14 E3 D1 D3 D16 A3 A4 A5 A8 A9 A13 A14 A16 A17 A18 B3 B5 B6 B7 B8 B9 B12 B13 B15 B16 B17 C1 C4 C5 C6 C7 C8 C9 C12 C13 C14 C15 C16 C17 C19 C20 D1 D5 D7 D9 D12 D14 D18 D19 D20 E1 E3 E4 E18 E20 F1 F2 F3 F18 I/O C32 I/O C30 I/O A11 I/O A10 I/O A9 I/O A6 I/O C34 I/O C31 I/O C29 I/O C28 I/O A12 I/O C27 I/O A16 I/O A15 I/O A14 I/O A13 I/O C26 I/O C25 I/O C24 I/O C23 I/O A19 I/O A17 I/O A18 I/O C22 I/O C21 I/O C20 I/O A20 I/O A21 I/O A22 I/O C18 I/O C17 I/O C19 I/O A23 I/O A24 I/O A25 I/O A26 I/O C13 I/O C14 I/O C15 I/O C16 I/O A27 I/O C12 I/O A28 I/O A29 I/O A31 I/O A34 I/O C6 I/O C9 I/O C10 I/O C11 I/O A30 I/O A32 I/O A35 Control Signal CLK/CLKEN MUXsel1 MUXsel2 MUXsel1 OE MUXsel1 MUXsel1 MUXsel2 OE CLK/CLKEN CLK/CLKEN MUXsel2 CLK/CLKEN MUXsel2 MUXsel1 OE MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel2 OE MUXsel1 MUXsel1 OE CLK/CLKEN CLK/CLKEN OE MUXsel1 MUXsel1 OE MUXsel2 MUXsel2 CLK/CLKEN OE MUXsel1 OE MUXsel1 MUXsel2 CLK/CLKEN MUXsel2 CLK/CLKEN CLK/CLKEN OE MUXsel2 MUXsel1 MUXsel1 OE MUXsel1 MUXsel2 MUXsel1 CLK/CLKEN MUXsel2 208 208 272 I/O PQFP fpBGA BGA Signal 144 142 14 13 12 9 146 143 141 140 16 138 21 20 19 18 136 135 134 133 24 22 23 132 131 130 26 27 28 127 126 128 29 30 31 32 122 123 124 125 34 120 36 37 39 42 113 116 117 118 38 40 43 E16 F14 F3 E1 E2 D2 E15 F15 F16 G13 F2 G15 G3 G2 G4 F1 G14 G16 H13 H15 H2 G1 H4 H16 H14 J16 H3 H1 J1 J15 J13 J14 J3 J2 J4 K1 K13 K15 K14 K16 K3 L16 K2 K4 L2 M2 N16 M16 L15 L14 L1 L3 M3 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H2 H19 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K17 K18 K19 L2 L3 L4 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N2 N19 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 I/O C5 I/O C7 I/O C8 I/O A33 I/O A37 I/O C0 I/O C3 I/O C4 I/O A36 I/O A38 I/O B0 I/O B10 I/O B17 I/O B22 I/O B30 I/O B36 I/O C2 I/O A39 I/O B1 I/O B3 I/O B6 I/O B9 I/O B12 I/O B14 I/O B18 I/O B21 I/O B25 I/O B31 I/O B34 I/O B37 I/O C1 I/O B2 I/O B7 I/O B11 I/O B15 I/O B19 I/O B20 I/O B24 I/O B28 I/O B32 I/O B35 I/O B38 I/O B4 I/O B5 I/O B8 I/O B13 I/O B16 I/O B23 I/O B26 I/O B27 I/O B29 I/O B33 I/O B39 Control Signal OE MUXsel2 CLK OE OE CLK/CLKEN MUXsel2 CLK/CLKEN CLK/CLKEN MUXsel1 CLK/CLKEN MUXsel1 OE MUXsel1 MUXsel1 CLK/CLKEN MUXsel1 MUXsel2 OE MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel1 MUXsel1 OE OE MUXsel2 MUXsel1 OE OE MUXsel1 MUXsel2 MUXsel2 MUXsel2 MUXsel2 CLK/CLKEN CLK/CLKEN CLK/CLKEN CLK/CLKEN MUXsel2 MUXsel1 CLK/CLKEN OE CLK/CLKEN OE CLK/CLKEN MUXsel2 MUXsel1 MUXsel2 OE OE MUXsel2 208 208 272 PQFP fpBGA BGA 112 114 115 41 46 106 109 111 45 47 50 61 70 84 94 101 108 48 51 53 57 60 64 67 71 83 87 95 98 102 107 52 58 62 68 72 82 86 92 96 99 103 55 56 59 66 69 85 88 90 93 97 104 N15 M14 M15 M1 N2 P14 N14 P16 N1 N3 P2 T4 T6 T10 P12 R14 R16 P1 R1 T1 R3 R4 R5 T5 N7 N9 N10 R12 T14 T15 P15 R2 P4 P5 R6 R7 R9 R10 R11 T13 P13 T16 P3 T2 T3 N6 P6 P10 T11 P11 T12 R13 R15 R18 R19 R20 T1 T3 T17 T18 T20 U1 U2 U3 U7 U9 U12 U14 U16 U20 V1 V2 V4 V5 V6 V7 V8 V9 V12 V13 V15 V16 V17 V20 W4 W5 W6 W8 W9 W12 W13 W15 W16 W17 W18 Y3 Y4 Y5 Y7 Y8 Y13 Y14 Y15 Y16 Y17 Y19 33 Specifications ispGDX160V/VA Signal Configuration: ispGDX160V/VA ispGDX160V/VA 272-Ball BGA Signal Diagram 20 A B C D E F G H J K L M N P R T U V W Y NC1 NC1 I/O C39 I/O C36 I/O C33 I/O C30 I/O C28 NC1 I/O C23 NC1 I/O C19 I/O C16 NC1 I/O C11 I/O C8 I/O C4 I/O C2 I/O C1 NC1 NC1 19 NC1 NC1 18 I/O D4 NC1 17 I/O D5 I/O D2 16 I/O D8 I/O D7 I/O D6 15 NC1 I/O D11 I/O D9 VCC 14 I/O D13 NC1 I/O D12 13 12 11 10 9 I/O D20 8 I/O D24 I/O D25 I/O D26 7 NC1 I/O D27 I/O D28 6 NC1 I/O D29 I/O D32 5 I/O D30 I/O D33 I/O D35 4 I/O D34 NC1 I/O D38 3 I/O D36 I/O D39 NC1 2 1 A B C D E F G H J K L M N P R T U V W Y Y3/ I/O 1 D16 TOE CLKEN3 NC NC1 GND NC1 NC1 NC1 NC1 I/O A7 I/O A10 I/O A12 I/O A15 I/O A17 I/O A20 I/O A24 I/O A27 I/O A29 I/O A32 NC1 I/O A38 I/O B1 NC1 NC1 NC1 I/O A1 I/O A2 I/O A4 I/O A8 I/O A11 NC1 I/O A16 I/O A19 NC1 I/O A23 NC1 I/O A28 I/O A30 I/O A33 I/O A36 I/O A39 NC1 NC1 I/O D15 I/O D14 I/O D19 I/O NC1 EPEN D21 I/O D22 I/O VCCIO I/O D1 VCC2 D3 I/O C38 NC1 I/O C32 I/O C29 I/O C27 I/O C24 I/O C20 I/O C17 I/O C15 I/O C12 I/O C10 I/O C7 NC1 NC1 NC1 NC1 I/O B39 I/O D0 I/O C37 Y2/ I/O NC1 D18 CLKEN2 RESET GND NC1 NC1 I/O I/O GND VCC D10 D17 I/O I/O I/O 1 D23 GND D31 VCC D37 GND NC I/O A0 I/O A3 I/O A5 I/O A9 I/O C35 VCC I/O C31 I/O C34 ispGDX160V/VA Bottom View GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC I/O A6 NC1 GND I/O C25 I/O C21 I/O C26 I/O C22 GND NC1 I/O A13 I/O A14 I/O VCC A18 I/O A22 I/O A26 I/O A21 I/O A25 I/O C18 VCC I/O C14 I/O C13 NC1 GND I/O C9 I/O C5 I/O C3 I/O C6 VCC I/O C0 GND NC1 I/O A34 I/O A31 I/O VCC A35 NC1 I/O I/O VCC B17 GND B10 VCC NC1 GND I/O B14 I/O B15 I/O B16 I/O B12 NC1 I/O B13 I/O B9 I/O B11 NC1 I/O B6 I/O B7 I/O B8 I/O B3 I/O B2 I/O B5 I/O A37 I/O B0 NC1 NC1 I/O B4 I/O I/O I/O NC1 GND B36 VCC B30 GND B22 TCK NC1 I/O B38 NC1 I/O B37 I/O B35 I/O B33 I/O B34 I/O B32 I/O B29 I/O B31 I/O B28 I/O B27 NC1 NC1 I/O B26 I/O B25 I/O B24 I/O B23 I/O I/O Y0/ B21 TMS CLKEN0 B18 I/O B20 TDO NC1 Y1/ I/O B19 TDI NC1 CLKEN1 NC1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1. NCs are not to be connected to any active signals, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. 34 Specifications ispGDX160V/VA Signal Configuration: ispGDX160V/VA ispGDX160V/VA 208-Ball fpBGA Signal Diagram 16 A B C D E F G H J K L M N P R T I/O D1 I/O D0 I/O C36 I/O C35 I/O C32 I/O C29 I/O C25 I/O C22 I/O C20 I/O C16 I/O C12 I/O C9 I/O C6 I/O C4 I/O C2 I/O B38 16 15 I/O D3 I/O D2 I/O C39 I/O C37 I/O C34 I/O C31 I/O C27 I/O C23 I/O C18 I/O C14 I/O C10 I/O C8 I/O C5 I/O C1 I/O B39 I/O B37 15 14 I/O D6 I/O D5 I/O D4 I/O C38 13 I/O D9 I/O D8 I/O D7 GND 12 I/O D13 I/O D11 I/O D10 VCC 11 I/O D17 I/O D15 I/O D14 I/O D12 10 NC 9 8 7 I/O D23 I/O D25 I/O D24 I/O D26 6 I/O D27 I/O D29 I/O D28 VCC 5 I/O D30 I/O D32 I/O D31 VCC 4 I/O D33 I/O D34 I/O D35 GND VCC VCC I/O A14 I/O A18 I/O A25 I/O A29 VCC VCC VCC I/O B30 I/O B31 I/O B29 12 VCC I/O B27 I/O B28 I/O B26 11 I/O B25 I/O B23 I/O B24 I/O B22 10 I/O I/O Y0/ B21 CLKEN0 B18 TDI TDO NC 1 3 I/O D36 I/O D38 I/O D37 I/O A5 I/O A8 I/O A11 I/O A16 I/O A20 I/O A23 I/O A27 I/O A32 I/O A35 I/O A38 I/O B4 I/O B6 I/O B8 3 2 I/O D39 I/O A0 I/O A2 I/O A6 I/O A9 I/O A12 I/O A15 I/O A19 I/O A24 I/O A28 I/O A31 I/O A34 I/O A37 I/O B0 I/O B2 I/O B5 2 1 I/O A3 I/O A1 I/O A4 I/O A7 I/O A10 I/O A13 I/O A17 I/O A21 I/O A22 I/O A26 I/O A30 I/O A33 I/O A36 I/O A39 I/O B1 I/O B3 1 A B C D E F G H J K L M N P R T 1 EPEN RESET Y2/ I/O I/O D18 CLKEN2 D21 Y3/ I/O I/O D19 CLKEN3 D20 I/O D16 TOE I/O D22 I/O VCCIO/ C33 VCC2 I/O C30 I/O C26 I/O C21 I/O C19 I/O C15 I/O C11 I/O C7 I/O C3 I/O C0 I/O B36 I/O B34 14 VCC I/O C28 I/O C24 I/O C17 I/O C13 VCC VCC GND I/O B35 I/O B33 I/O B32 13 ispGDX160V/VA Bottom View GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O B13 I/O B16 I/O B15 I/O B17 6 VCC I/O B11 I/O B12 I/O B14 5 GND I/O B7 I/O B9 I/O B10 4 Y1/ I/O I/O B20 CLKEN1 B19 TCK 9 TMS 8 NC 7 1 1. NCs are not to be connected to any active signals, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. 35 Specifications ispGDX160V/VA Pin Configuration: ispGDX160V/VA ispGDX160V/VA 208-Pin PQFP Pinout Diagram I/O D 39 MUXsel2 I/O D 38 MUXsel1 I/O D 37 OE I/O D 36 CLK/CLKEN GND -- I/O D 35 MUXsel2 I/O D 34 MUXsel1 I/O D 33 OE I/O D 32 CLK/CLKEN I/O D 31 MUXsel2 I/O D 30 MUXsel1 I/O D 29 OE I/O D 28 CLK/CLKEN GND -- I/O D 27 MUXsel2 VCC -- I/O D 26 MUXsel1 I/O D 25 OE I/O D 24 CLK/CLKEN I/O D 23 MUXsel2 I/O D 22 MUXsel1 I/O D 21 OE I/O D 20 CLK/CLKEN RESET -- VCC -- EPEN -- GND -- Y3/CLK_EN3 -- Y2/CLK_EN2 -- NC1 -- TOE -- I/O D 19 MUXsel2 I/O D 18 MUXsel1 I/O D 17 OE I/O D 16 CLK/CLKEN I/O D 15 MUXsel2 I/O D 14 MUXsel1 I/O D 13 OE VCC -- I/O D 12 CLK/CLKEN GND -- I/O D 11 MUXsel2 I/O D 10 MUXsel1 I/O D 9 OE I/O D 8 CLK/CLKEN I/O D 7 MUXsel2 I/O D 6 MUXsel1 I/O D 5 OE I/O D 4 CLK/CLKEN GND -- I/O D 3 MUXsel2 I/O D 2 MUXsel1 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 Data Control Control -- CLK/CLKEN OE MUXsel1 MUXsel2 -- CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 -- CLK/CLKEN -- OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 -- CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 -- MUXsel2 -- CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 -- CLK/CLKEN OE MUXsel1 MUXsel2 -- CLK/CLKEN OE MUXsel1 Data VCC I/O A 0 I/O A 1 I/O A 2 I/O A 3 GND I/O A 4 I/O A 5 I/O A 6 I/O A 7 I/O A 8 I/O A 9 I/O A 10 I/O A 11 GND I/O A 12 VCC I/O A 13 I/O A 14 I/O A 15 I/O A 16 I/O A 17 I/O A 18 I/O A 19 GND I/O A 20 I/O A 21 I/O A 22 I/O A 23 I/O A 24 I/O A 25 I/O A 26 VCC I/O A 27 GND I/O A 28 I/O A 29 I/O A 30 I/O A 31 I/O A 32 I/O A 33 I/O A 34 I/O A 35 GND I/O A 36 I/O A 37 I/O A 38 I/O A 39 VCC I/O B 0 I/O B 1 I/O B 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Data 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VCCIO/VCC2 I/O D1 I/O D 0 VCC I/O C 39 I/O C 38 I/O C 37 I/O C 36 GND I/O C 35 I/O C 34 I/O C 33 I/O C 32 I/O C 31 I/O C 30 I/O C 29 I/O C 28 GND I/O C 27 VCC I/O C 26 I/O C 25 I/O C 24 I/O C 23 I/O C 22 I/O C 21 I/O C 20 GND I/O C 19 I/O C 18 I/O C 17 I/O C 16 I/O C 15 I/O C 14 I/O C 13 VCC I/O C 12 GND I/O C 11 I/O C 10 I/O C 9 I/O C 8 I/O C 7 I/O C 6 I/O C 5 I/O C 4 GND I/O C 3 I/O C 2 I/O C 1 I/O C 0 VCC Control -- OE CLK/CLKEN -- MUXsel2 MUXsel1 OE CLK/CLKEN -- MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN -- MUXsel2 -- MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN -- MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE -- CLK/CLKEN -- MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN -- MUXsel2 MUXsel1 OE CLK/CLKEN -- ispGDX160V/VA Top View 1. No Connect Pins (NC) are not to be connected to any active signal, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. I/O B 3 MUXsel2 GND -- I/O B 4 CLK/CLKEN I/O B 5 OE I/O B 6 MUXsel1 I/O B 7 MUXsel2 I/O B 8 CLK/CLKEN I/O B 9 OE I/O B 10 MUXsel1 I/O B 11 MUXsel2 GND -- I/O B 12 CLK/CLKEN VCC -- I/O B 13 OE I/O B 14 MUXsel1 I/O B 15 MUXsel2 I/O B 16 CLK/CLKEN I/O B 17 OE I/O B 18 MUXsel1 I/O B 19 MUXsel2 1NC -- 1NC -- CLK_EN0/Y0 -- CLK_EN1/Y1 -- GND -- TDO -- TMS -- TCK -- TDI -- I/O B 20 CLK/CLKEN I/O B 21 OE I/O B 22 MUXsel1 I/O B 23 MUXsel2 I/O B 24 CLK/CLKEN I/O B 25 OE I/O B 26 MUXsel1 VCC -- I/O B 27 MUXsel2 GND -- I/O B 28 CLK/CLKEN I/O B 29 OE I/O B 30 MUXsel1 I/O B 31 MUXsel2 I/O B 32 CLK/CLKEN I/O B 33 OE I/O B 34 MUXsel1 I/O B 35 MUXsel2 GND -- I/O B 36 CLK/CLKEN I/O B 37 OE I/O B 38 MUXsel1 I/O B 39 MUXsel2 Control Data 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 36 Specifications ispGDX160V/VA Part Number Description ispGDX XXXXX - X XXXX X Device Family Device Number 160V 160VA Speed 3 = 3.5ns Tpd 5 = 5ns Tpd 7 = 7ns Tpd 9 = 9ns Tpd Grade Blank = Commercial I = Industrial Package Q208 = 208-Pin PQFP B208 = 208-Ball fpBGA B272 = 272-Ball BGA 0212/ispGDXVA Ordering Information COMMERCIAL FAMILY tpd (ns) 3.5 3.5 3.5 5 ispGDXVA 5 5 7 7 7 5 5 5 ispGDXV* 7 7 7 ORDERING NUMBER ISPGDX160VA-3Q208 ispGDX160VA-3B208 ispGDX160VA-3B272 ispGDX160VA-5Q208 ispGDX160VA-5B208 ispGDX160VA-5B272 ispGDX160VA-7Q208 ispGDX160VA-7B208 ispGDX160VA-7B272 ispGDX160V-5Q208 ispGDX160V-5B208 ispGDX160V-5B272 ispGDX160V-7Q208 ispGDX160V-7B208 ispGDX160V-7B272 PACKAGE 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA Table 2-0041A/ispGDXV/A INDUSTRIAL FAMILY tpd (ns) 5 5 5 7 ispGDXVA 7 7 9 9 9 ispGDXV* 7 ORDERING NUMBER ispGDX160VA-5Q208I ispGDX160VA-5B208I ispGDX160VA-5B272I ispGDX160VA-7Q208I ispGDX160VA-7B208I ispGDX160VA-7B272I ispGDX160VA-9Q208I ispGDX160VA-9B208I ispGDX160VA-9B272I ispGDX160V-7Q208I PACKAGE 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA 208-Pin PQFP Table 2-0041C/ispGDXV *Use ispGDX160VA for new designs. Note: The ispGDX160VA devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, e.g. ispGDX160VA-3B208-5I. 37 |
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